1. Field of the Invention
The invention relates to an address matching circuit for redundancy cell repair in DRAM memories, and more particularly to such a circuit which is without a DC path at power up and one which has a better margin when the fuse in the circuit is only partially blown.
2. Description of the Related Art
Referring now to FIG. 1a a conventional fuse control logic circuit 10 is shown. Power-up signal PU is the input to control section 12 and couples to the gate of PMOS transistor P2. Transistors P1 and P2 are coupled in parallel between a power supply VCC and a common node P2D. The fuse section 14 with fuse I1 is coupled between P2D and the return terminal of power supply VCC (ground in FIG. 1a). The common node P2D couples to the gates of PMOS transistor P3 and NMOS transistor N1 of driver section 16. Transistors P3 and N1 are coupled in series between VCC and the return terminal of power supply VCC (ground). The junction between transistors P3 and N1 is the output terminal OUT of driver section 16. The output terminal OUT also feeds back to the gate of PMOS transistor P1.
The problem with the related art of FIG. 1a is that it has a DC path when PU=0 (logical “0”), which is the power-up state. This will introduce potential problems such as excessive current drain if there are many of these circuits, especially when the driving capability of the power supply is not enough. An additional problem is that the related art circuit has a smaller margin for normal function if fuse I1 is not perfectly blown because transistor P2 represents a large resistor for a small DC current. Common node P2D will then be at some intermediate voltage level depending on the resistance of fuse I1. As a result the circuit may malfunction because the voltage at common node P2D is not high enough. Additionally, there may be DC current flowing through transistors P3/N1. This is a serious problem for low power memories which may be out-of-spec then.
The related art circuit 11 of FIG. 1b is structurally similar to circuit 10 of FIG. 1a but uses NMOS transistors. Fuse section Block 14 is coupled between power supply VCC and node N2D. Block 22, coupled between node N2D and ground comprises transistors N21 and N22. The first input of Block 22 receives power-up signal PU-bar, which is the inverted signal of PU of circuit 10, Block 12. Block 26, showing a generic inverter INV, is coupled between node N2D and the second input to Block 22. The description for FIG. 1a above applies equally to circuit 11 of FIG. 1b. 
FIG. 2 is a graph of the input signal and the voltage levels of a good power supply or regulator during power-up of the circuit of FIG. 1. Curve 21 depicts the external VDD supply ramping up, Curve 22 depicts the power-up signal PU ramping up briefly to Point A, dropping to “0” level, and then rising at Point B to join Curve 21. Curve 23 depicts the internal VCC supply ramping up smoothly.
FIG. 3 is a graph of the input signal and voltage levels of a bad power supply or regulator of the circuit of FIG. 1. Curves 31 and 32 are identical to Curves 21 and 22 of FIG. 2. Internal VCC Curve 33, however, ramps up only to about Point A, then continues almost horizontally to Point C and then rises. The section from near Point A to Point C represents an excessive current draw caused by DC paths in the P2/I1 path in other circuits without blown fuses. This delay in the rise of the internal VCC supply causes problems when the blown-fuse initialization time is not long enough, because then common node P2D cannot set up properly at startup and its voltage level is at an indeterminate state. An improper address may be output or an improper function/timing option may be selected. Conversely, if the initialization time is lengthened it affects other circuits which use the power-up signal PU and VCC for initialization. Lastly, in blown fuse circuits a DC current path can be introduced in the P3/N1 transistor path because P2D is neither at “0” nor at “1”.
An improved circuit and method are clearly needed to overcome these problems of the related art. The circuits and method described hereinafter and illustrated in FIGS. 4a, 4b, 5a, 5b, and 6 completely eliminates these problems.
U.S. Pat. No. 6,292,422 (Pitts) discloses a system and method for storing data values by implementation of electrical fuse chains which enables the programming and use of electrical fuses and includes read and write protection. U.S. Pat. No. 6,073,258 (Wheater) teaches the use of fuse elements responsible for soft-fusing redundant memory elements into the memory array. Soft-fusing is defined to mean that the fuse elements may be set and reset via an electronic signal.
It should be noted that none of the above-cited examples of the related art address the above described problems.